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2023.06.21
Jim Chang took the stage at the 2023 TSMC Technology Symposium to talk about 3Dblox, a standard to address the rising complexity of 3D IC design and unify the design ecosystem with qualified EDA tools and flows for TSMC 3DFabric technology. The modularized 3Dblox standard is designed to model, in one format, the key physical stacking and the logical connectivity information in 3D IC designs. TSMC has worked with EDA partners in the 3DFabric alliance to enable 3Dblox for every aspect of 3D IC designs, including physical implementation, timing verification, physical verification, electro-migration IR drop (EMIR) analysis, thermal analysis, and more. TSMC 3Dblox is designed to maximize flexibility and ease of use, offering ultimate 3D IC design productivity.

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Press Release
2023.09.27
SAN JOSE, Calif.— Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of new system prototyping flows based on the Cadence® Integrity™ 3D-IC Platform that support the 3Dblox 2.0 standard. The Integrity 3D-IC Platform is fully compliant with the 3Dblox 2.0 standard language extensions, and the flows have been optimized for all of TSMC’s latest 3DFabric™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS) and System-on-Integrated-Chips (TSMC-SoIC) technologies. Through this latest collaboration between Cadence and TSMC, customers creating AI, mobile, 5G, hyperscale computing and IoT 3D-IC designs can model system prototypes to accelerate design turnaround time.

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2023.09.27
SUNNYVALE, Calif., Sept. 27, 2023 /PRNewswire/ – Synopsys, Inc. (Nasdaq: SNPS) today announced it is extending its collaboration with TSMC to advance multi-die system designs with a comprehensive solution supporting the latest 3Dblox 2.0 standard and TSMC’s 3DFabric™ technologies. The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC’s leading N3E process for seamless die-to-die connectivity.

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2023.04.26
SAN JOSE, Calif.— Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced new design flows based on the Cadence; Integrity™ 3D-IC platform to support the TSMC 3Dblox™ standard for 3D front-end design partitioning in complex systems. Through this latest collaboration, the Cadence flows are optimized for all of TSMC’s latest 3DFabric™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS;) and System-on-Integrated-Chips (TSMC-SoIC) technologies. By using these design flows, customers can accelerate the development of advanced multi-die package designs for emerging 5G, AI, mobile, hyperscale computing and IoT applications.

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Events
2023.10.12
The 3rd 3DFabric Alliance Workshop includes a TSMC presentation with the latest 3Dblox 2.0 status, which is a major milestone that enables feasibility study features for prototyping.

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2023.04.27
It was held on the next day of 2023 TSMC technology Symposium with 20 members.
In addition to TSMC and partner presentations, there were two customer presentations that shared their perspectives of 3DIC design challenges for pointing the directions under the scope of 3DFabric Alliance collaboration among members.

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2023.02.10
The first All-Partners meeting with 19 founding members after the official announcement of 3DFabric Alliance in October 2022 at TSMC OIP Ecosystem Forum.
There were TSMC presentations on 3DFabric technology, 3Dblox status and 3DIC Testing Trend & Challenges, as well as partner presentations by IBIDEN, Samsung Memory, Cadence and Synopsys on EDA & IP respectively.

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